/*
******************************************************************************
File:     main.c
Info:     Generated by Atollic TrueSTUDIO(R) 9.2.0   2022-05-12

The MIT License (MIT)
Copyright (c) 2018 STMicroelectronics

Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:

The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.

THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.

******************************************************************************
*/

/* Includes */
#include "stm32f4xx.h"
#include "stm32f4xx_rcc.h"
#include "stm32f4xx_gpio.h"

#define MASK(x) (1U << (x))
volatile unsigned int* GPIO_D = (unsigned int*)0x40020C00;
volatile unsigned int* GPIO_D_MODER_reg = (unsigned int*)0x40020C00;
volatile unsigned int* GPIO_D_ODR_reg = (unsigned int*)(0x40020C14);
volatile unsigned int* RCC_AHB1ENR_reg = (unsigned int*)(0x40023830);

/* Private macro */
/* Private variables */
/* Private function prototypes */
/* Private functions */

/**
**===========================================================================
**
**  Abstract: main program
**
**===========================================================================
*/
int main(void)
{
  int i = 0;
  uint16_t result = 0;

  /**
  *  IMPORTANT NOTE!
  *  The symbol VECT_TAB_SRAM needs to be defined when building the project
  *  if code has been located to RAM and interrupts are used. 
  *  Otherwise the interrupt table located in flash will be used.
  *  See also the <system_*.c> file and how the SystemInit() function updates 
  *  SCB->VTOR register.  
  *  E.g.  SCB->VTOR = 0x20000000;  
  */

  RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOD, ENABLE);
  GPIO_InitTypeDef GPIO_InitStructure;
  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_15 | GPIO_Pin_14 | GPIO_Pin_13 | GPIO_Pin_12; //pin 15 se konfigurira
  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
  GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
  GPIO_Init(GPIOD, &GPIO_InitStructure);

  RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOB, ENABLE);
  GPIO_InitTypeDef GPIO_InitStructADC;
  GPIO_InitStructADC.GPIO_Mode = GPIO_Mode_AN;
  GPIO_InitStructADC.GPIO_Pin = GPIO_Pin_1;
  GPIO_InitStructADC.GPIO_PuPd = GPIO_PuPd_NOPULL;
  GPIO_Init(GPIOB, &GPIO_InitStructADC);


  RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1, ENABLE);
  ADC_InitTypeDef ADC1_InitStruct;
  ADC1_InitStruct.ADC_Resolution = ADC_Resolution_12b;
  ADC1_InitStruct.ADC_ScanConvMode = DISABLE;
  ADC1_InitStruct.ADC_ContinuousConvMode = DISABLE;
  ADC1_InitStruct.ADC_ExternalTrigConv = DISABLE;
  ADC1_InitStruct.ADC_ExternalTrigConvEdge = ADC_ExternalTrigConvEdge_None;
  ADC1_InitStruct.ADC_DataAlign = ADC_DataAlign_Right;
  ADC1_InitStruct.ADC_NbrOfConversion = 1;
  ADC_Init(ADC1, &ADC1_InitStruct);
  ADC_RegularChannelConfig(ADC1, ADC_Channel_9, 1, ADC_SampleTime_84Cycles);
  ADC_Cmd(ADC1, ENABLE);

  /* TODO - Add your application code here */

  /* Infinite loop */
  while (1)
  {
	  ADC_SoftwareStartConv(ADC1);
	  while (!ADC_GetFlagStatus(ADC1, ADC_FLAG_EOC));
	  result = ADC_GetConversionValue(ADC1);
	  if(result < 1024 && result > 5)
	  {
		  *GPIO_D_ODR_reg |= MASK(15);
		  *GPIO_D_ODR_reg &= ~MASK(14);
		  *GPIO_D_ODR_reg &= ~MASK(13);
		  *GPIO_D_ODR_reg &= ~MASK(12);
	  } else if(result < 2048)
	  {
		  *GPIO_D_ODR_reg |= MASK(15);
		  *GPIO_D_ODR_reg |= MASK(14);
		  *GPIO_D_ODR_reg &= ~MASK(13);
		  *GPIO_D_ODR_reg &= ~MASK(12);
	  } else if(result < 3072)
	  {
		  *GPIO_D_ODR_reg |= MASK(15);
		  *GPIO_D_ODR_reg |= MASK(14);
		  *GPIO_D_ODR_reg |= MASK(13);
		  *GPIO_D_ODR_reg &= ~MASK(12);
	  } else
	  {
		  *GPIO_D_ODR_reg |= MASK(15);
		  *GPIO_D_ODR_reg |= MASK(14);
		  *GPIO_D_ODR_reg |= MASK(13);
		  *GPIO_D_ODR_reg |= MASK(12);
	  }
  }
}